Custom IC Design

 Custom IC Design/Full Custom/Analog IC Design

Custom IC Design is the process of designing  the chip from the transisitor level to the signoff process.it can aslo be reffered as ASIC(Application Specific Integrated Circuits) Full Custom Design.CMOS Digital Design from schematic to GDS II will also be in same flow.Full custom design is also used for designing the standard cell for semicustom design.

In this Section you will able to learn how to design full custom design using Virtuoso tool flow,you have to just follow the page.

Before going to the Virtuoso tool,you will able to learn some of design steps of ASIC Full Custom Design.

Specification:-This is the first step of any design process.In this Stage product marketers, operation managers or designers define the overall goal and high level requirements of the system.Factors to be considered in this process are 

• Performance
• Functionality
• Physical Dimension(die size)
• Fabrication technology and design technique are also considered.

The end results are specifications for the size, speed, power, and functionality of the VLSI system. 

Schematic Design:-The schematic design entry can be achieved by basically two method  one is by HDL(Hardware Description Languages) entry and others is Schematic entry.In full custom Design we capture our design by schematic entry and routing them.In semicustom design we design our our circuit by HDLs either by verilog or vhdl.

For understanding purpose,Figure below show the schematic design of INVERTER designed in Virtuoso Schematic editor tool.

           

    Different Eda Vendors Tools for Schematic Design.

• Virtuoso Schematic Editor by Cadence
• ICstudio by Mentor Graphics
• cosmosSE by Synopsys    

Simulation:- Simulation is the process of verify the schematic Design by adding some additonal sources to designed schematic and observe that does our designed provide required output or specification what we wanted is achieved or not.Cadence provide spectre multi mode simulation tool for the simulation of circuit.if we get the desired output we move to the further step layout design.

for understanding purpose,suppose we have designed Simple INVERTER so will check that is it giving output 1 when input 0 and output 0 when input 1.

Test Circuit to Test the inverter Functionality

transient response analysis

Layout Design:- After verifying the functionality and specification of our design we move to next step know as layout design.Layout is process of designing the physical layer of schematic.in layout we design different layer like polysilicon layer,different metal layer,contacts,via to cnnect two different wire connection.In Vlsi field Analog layout or STANDARD cell layout design is field in which you can make your bright career.in this step we also used routing different routing technique to rout the connection between the circuit.we follow the layout design rule provided by foundry so that the our design can be fabricated.after the layout design we move to the verification step known as physical verification.

figure below show the layout of inverter for understanding perpose.we are taking inverter because it basic block we start our design if we understand its designing it will be easy to desigin other circuit.

 

layout design of inverter

Physical Verification:- The physical verification basically check the correctness of the layout design.physical verification includes DRC(Design Rule Check),LVS(Layout Vs Schematic) Check,Antenna Rule check,Electrical Rule Check.

• Design Rule Check (DRC):- DRC verify that the layout you designed is meeting the technology imposed contraints or not. DRC also erifies layer density for chemical-mechanical polishing (CMP).
  
  
  
   
• Layout vs Schematic (LVS):-LVS verifies the functionality of the design. From the layout, a netlist is derived and compared with the original netlist produced from logic synthesis or circuit design. In LVS different violation are solved like
• open error
• short error
• device mismatch
• port mismatch
• instance mismatch
• net mismatch
• floating nets

• Antenna Rule Checking:-Antenna rule checking seeks to prevent antenna effects, which may damage transistor gates during manufacturing plasma-etch steps through accumulation of excess charge on metal wires hat are not connected to PN-junction nodes.

• Electrical Rule Check:-Electrical rule checking (ERC) verifies the correctness of power and groundconnections, and that signal transition times (slew), capacitive loads and fanouts are appropriately bounded.

RC Extraction:- RC extraction can also be referred as parasitic extraction. Parasitic extraction is the calculation of all routed net capacitances and resistances for the purpose of delay calculation, static timing analysis, circuit simulation, and signal integrity analysis.

or in easy way you can understand like, The conductor (copper wire) used for routing purpose has parasitic(Resistance and capacitance, RC) due to which there will be some delay in wire called wire delay so inPEX we find the value RC. Tool used is Synopsys, Star XC. The required input file is netlist obtained from APR, Rule file & mapping file, both the rule file and mapping file is provided by the fabrication house. The output of PEX is SPEF/SDF file.

Parasitic extraction is performed by analyzing each net in the design and taking into account the effects (such as dielectric stack) of the net’s own topology and proximity to other nets. Currently, most physical design tools are using three-dimensional (3D) models to extract capacitance associated

with each net.

GDS II:- After the successful ananlysis of previous steps GDS II file is generated. GDS II refers to Graphical Data Stream Information Interchange. GDS file contain the physical layout information. The final GDS file (a binary database file format which is the default industry standard for data exchange of integrated circuit or IC layout artwork) is normally send to a foundry which fabricates the silicon. Once fabricated, proper packaging is done and the chip is made ready for testing.

 

    

 This is full flow of custom IC Design you can go through it to learn.