Verilog

Introduction to Verilog

Verilog is the most popular language for the digital circuit design and logic design. Verilog is standardized as IEEE 1364, as Hardware Description Language(HDL) For Digital Design.

Verilog Syntax

Before starting how to write Verilog code for the digital circuits, we have to go through some of syntax used to write better the code.

  • whitespace are ignored during simulation.
  • for comments we can use either //...........(for single line comment) or /*...........*/(for double line comment)
  • Identifiers are the words used to identify names, variable and Function.it can be a sequence letters, digits, underscore( _ ) and dollar sign( $ ).Identifiers are the case sensitive. we will understand it properly when we will write code.

  • Keywords can't be used as identifiers. keywords must be a lower case characters.         Example of Keywords:- reg, wire, and, or, assign, case, while, nand, module etc.
  • Number Literals representation in Verilog
literals
        In general Representation:- size_in_bits ' base Number.
        For improved readability we can add underscore like 16'hb2_54

Verilog Logic Value System

Verilog consist of fours basics value. These are 0, 1, X, Z.

  • 0 (logic zero or false condition)

  • 1 (logic one or true condition)

  • X (unknown value or contention)

  • Z (high impedance state or floating)

The X can also be accepted as x and Z can be accepted as z in verilog.

Verilog Structure

Verilog structure start with module and end with end module as shown below. Module has module name, list of input/output port, declaration and functional specification.

Figure: Verilog Code Structure



For better understanding I will show you the Verilog code for OR gate and its generated design from the code.


Verilog Data Types

Data types available in Verilog are

nets:-

  • it represents the connection between hardware element
  • nets must be driven continuously
  • net is used to wire up the instantiation
  • net includes wire, wor, tri and wand

registers:-

  • Registers retain the last value assigned
  • it is generally used to represent the storage elements
  • it includes types reg and integer
reg

wire

integer

real

time

parameter

event





 

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