Physical Design Engineer | MosChip Semiconductor Technology Ltd

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Job Summary

As a member of the Physical Design team, the PD Engineer will be responsible for building next-generation state-of-the-art networking chips in advanced process node. The PD Engineer will drive the backend process of the entire Implementation flow including hierarchical floor planning, placeroute, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance die size optimization.

Job Description:- 

  • Responsible for all aspects of Physical Design for Full chip/Blocks covering Floorplanning, Budgeting, Clock Tree planning analysis, Placement, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis fixes, Low Power solution development implementation.
  • Responsible for full development flow: Floorplanning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off

Skills Required:-

  • Exp: 3-4 Years in Physical Design Engineer
  • Languages: Hands on Experience in TCL, PERL
  • Experience of block-level place and route including PG Planning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
  • Work experience with node 7nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias.
  • Experience with Low Power Design Voltage Islands, Power Gating, Substrate-bias techniques.
  • Experience with ASIC Physical Design: Floorplanning, PR, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
  • Experience with Static Timing Analysis in Primetime or Primetime-SI.
  • Excellent understanding and hands-on experience with physical verification (DRC/LVS/ERC/antenna)
  • Good to have Timing closure on high-speed interfaces is a plus. 
  • Excellent communication skills.

Apply Link:-  

https://moschip.com/careers/physical-design-engineer/




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