Basics VLSI Interview Questions

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  •  What Moore's Law Predicts?

In 1965, Gordon Moore predicted that the number of transistors on a chip doubles every 18 to 24 months. He also predicted that semiconductor technology will double its effectiveness every 18 months and many other factors grow exponentially.”

  • Full Custom and Semi Custom Difference
  • What are different VLSI Design Styles?
  1. Field Programmable Gate Array(FPGA)
  2. Gate Array Design
  3. Full Custom Design
  4. Semi Custom Design 

  • What do you mean by Standard Cell?

Standard Cells are the predesigned,pretested and precharacterised cell used in the ASIC Design to make circuits.Example of Standard Cells are AND ,OR ,NOR, XOR,NOT,MUX etc.

  •  What is Synthesis in Verilog?

Synthesis is the process of converting the verilog/VHDL code into Gate level Netlist.Different tool used for synthesis are:- Genus by Cadence, Design Compiler by Synopsys.

 



         

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