Job Role- Digital Verification Engineer
Skills & Qualification:-
- Experience in the range of 1-3 years.
- Experience with mixed signal designs is a plus – understanding of modelling of Analog functions and digital mixed signal in C, Python, Matlab is a plus.
Function & Responsibilty:-
- Development of test benches and tests for module level testing.
- Development of tests for top level using System Verilog and UVM methodologies.
- Putting together test plans for module and top level.
- Running code and functional coverage.
- Run Gate level simulations at module and top level.
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