Job Description:
- Understand the Design intent from the IP DOS and extract verification requirements / test cases
- Set up the UVM-based testbench for the IP and implement functional coverage
- Implement simulation tests, run and debug simulations of these tests against the RTL of the IP
- Report DOS / RTL defects and track them to closure; update verification collateral whenever design features get updated
- Achieve 100% functional coverage against the verification requirements
- Familiarity with Unix / Linux and SystemVerilog / OOPs is preferred.
- Good communication skills
Qualification : Bachelor's Degree/M.tech/Trained Engineer in Verification field
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